About the role
seeking an RTL Design Engineer for a fully remote 12-month contract engagement focused on custom silicon development. The ideal candidate will own the full micro-architecture and RTL design lifecycle for complex digital blocks, operating independently from day one. This role requires hands-on fluency in SystemVerilog and recent experience with memory controller design and SoC integration.
Responsibilities
Own micro-architecture definition derived from high-level functional specifications
Develop and implement RTL for complex digital blocks using SystemVerilog/Verilog
Drive digital block control logic and IP integration
Participate in subsystem-level architecture alignment discussions
Support design sign-off activities including CDC, RDC, lint, and synthesis readiness checks
Collaborate closely with Design Verification (DV) teams for closure and debug
Take full project lifecycle ownership with minimal supervision
Key Qualifications
Strong, current expertise in RTL design using SystemVerilog and/or Verilog
Demonstrated ability to independently define micro-architecture from functional specs
Recent hands-on experience designing custom RTL blocks such as controllers, DMAs, or SoC bus bridges
Solid understanding of memory controllers, including HBM, DDR4, or DDR5
Experience with SoC integration and digital subsystem design
Proficiency with IP integration and block-level ownership
Working knowledge of sign-off flows including CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing)
Experience designing IPs with multiple clock domains
Ability to operate independently with no ramp-up time required
Preferred Qualifications
Experience in subsystem-level RTL development
Exposure to Die-to-Die (D2D) logic design
Prior experience working directly with major hyperscaler silicon teams
Originally posted on Himalayas