About the role
About the job
Mercor connects elite creative and technical talent with leading AI research labs. Headquartered in San Francisco, our investors include Benchmark, General Catalyst, Peter Thiel, Adam D'Angelo, Larry Summers, and Jack Dorsey.
Position: RTL Design Engineers
Type:Contract
Compensation:$100–$175/hour
Location:Remote
Duration:3+ months
Commitment:40 hours/week
Role Responsibilities
Evaluate digital chip design workflows to enhance AI model training and evaluation.
Design and verify RTL components using Verilog/SystemVerilog.
Collaborate with architecture, verification, and implementation teams to improve model outputs.
Develop reusable verification components and testbench infrastructure.
Leverage LLM-based tools to accelerate chip design and verification processes.
Work independently and asynchronously to meet project deadlines.
Qualifications
Must-Have
3–10 years of experience in digital RTL design or design verification.
Strong proficiency in Verilog/SystemVerilog and UVM.
Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocols.
Experience with ASIC design flows and common EDA tools.
Ability to write clear design documentation and communicate technical tradeoffs.
Preferred
Knowledge of AMBA protocols (AXI, AHB, APB).
Background in CPU, GPU/ML accelerator, networking, memory subsystem, PCIe/high-speed IO, SoC interconnect, low-power design.
Exposure to formal verification or SV/UVM-based design verification.
Start Date
Week of 04/23; applications reviewed on a rolling basis.
Compensation & Legal
Hourly contractor, Paid weekly.
Application Process (Takes 20–30 mins to complete)
Upload resume
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Resources & Support
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PS: Our team reviews applications daily. Please complete your AI interview and application steps to be considered for this opportunity.
Originally posted on Himalayas