About the role
Bolt Graphics is a semiconductor startup based in Sunnyvale, CA building the fastest and most efficient graphics processors. We pride ourselves on our first principles approach to solving problems. We are energized by our mission to reduce the barrier of entry for content creation and consumption. Our goal is to enable everyone to easily create, simulate and consume immersive experiences as vividly as they can imagine them.
Our Values
Be Fearless:Unmute yourself. Test boundaries and get proven right.
Remain Adaptable:Stay comfortable in a continuously changing world. If you’re wrong, concede and move on.
Educate Your Ego:Selflessly collaborate towards our shared purpose.
About the role:
As a Staff / Senior Staff Physical Design Engineer, you will be responsible for driving full-chip or block-level physical implementation from netlist to GDSII. You will play a critical role in achieving timing, power, and area (PPA) targets while ensuring high-quality tapeouts.
What you'll do:
Own end-to-end physical design flow: synthesis support, floorplanning, placement, CTS, routing, and signoff
Drive timing closure (setup/hold) across multiple PVT corners using advanced STA methodologies (OCV/POCV)
Perform and debug DRC/LVS/EM/IR issues and drive clean signoff
Work closely with RTL, architecture, and verification teams for design convergence
Handle ECO flows, including late-stage timing and functional fixes
Optimize designs for power, performance, and area (PPA)
Integrate and validate hard macros (SRAMs, IOs, analog blocks)
Support GLS, SDF generation, and debug timing-related issues
Develop and enhance automation scripts (TCL/Python) for PD flows
Collaborate with foundry/vendor teams during tapeout and signoff
Required Qualifications:
Bachelor’s/Master’s degree in Electrical Engineering or related field
8–12 years of experience in ASIC physical design
Proven experience in full-chip or large block implementation and tapeouts
Strong expertise in:
Floorplanning and power planning
Placement, CTS, routing, and physical verification
Static Timing Analysis (STA) and timing closure
Hands-on experience with industry-standard tools such as:
Synopsys ICC2 / Cadence Innovus
Synopsys PrimeTime
Mentor Calibre
Experience with advanced nodes (7nm and below preferred)
Strong debugging and problem-solving skills
Preferred Qualifications:
Experience with low-power design techniques (UPF/CPF)
Knowledge of EMIR analysis (e.g., Ansys RedHawk-SC)
Familiarity with multi-voltage designs and power domains
Experience with high-speed interfaces or complex SoCs (CPU/GPU/AI)
Exposure to GLS and timing-related silicon debug
Scripting expertise in Python/TCL
Bolt is committed to building a diverse and inclusive environment in which we recognize and value each other’s differences as well as fostering a culture that promotes its core values: Professionalism, Integrity, and Respect. As an equal opportunity employer, all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, genetic information, national origin, age, disability, or status as a protected veteran.
Originally posted on Himalayas